From a196e9984407db34778d6ebd504ed325d548a39d Mon Sep 17 00:00:00 2001
From: Cayetano Santos <cayetano.santos@apc.univ-paris7.fr>
Date: Mon, 9 Apr 2018 09:04:12 +0200
Subject: [PATCH] slight documenting comment in top.org

---
 src-vorg/top.org | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src-vorg/top.org b/src-vorg/top.org
index 5a4e8cc..11fb251 100644
--- a/src-vorg/top.org
+++ b/src-vorg/top.org
@@ -1060,7 +1060,8 @@ Anyway, I don’t have space for it in the fpga.
 **** Juno                                                         :xilinx:
 
 The multiplexor, to send data from =nb_asics= modules to the [[*USB Interface][USB Interface]]. I do
-use =extend= here, so the data i/o data bus width is not respected.
+use =extend= here, so the data i/o data bus width is not respected: at the output,
+we bet one more byte including the asic number from where the data originates.
 
 #+begin_src vhdl-tools
   U_catiroc_usb_if_sc : catiroc_usb_if
-- 
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