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1.5.3

936a097a · Redimension fifos to use al fpga resources · 6 years ago
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1.5.2

dd0da5ff · Merge branch 'p2_params_reordering' · 6 years ago
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1.5.1

786e2787 · Merge branch 'boardid-optimize' · 6 years ago
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1.5

66004f18 · tangled for omega test and compiled · 6 years ago
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1.4.2

eff6328a · fixed issue in cati data capture · 7 years ago
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1.4.1

3bcfc1da · S-Curve : use falling edge, and not levels to compute · 7 years ago
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1.4

c6ce9271 · Merge branch 'format-v3' · 7 years ago
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1.3

305ef23d · removed multiplexor after catiroc module with altera · 7 years ago
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1.2

d950fd54 · xilinx: compiled project · 7 years ago
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1.1

2d39ce86 · Fixed doc un usb if vorg file · 7 years ago
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1.0

79e652f2 · fixed last commit · 7 years ago
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0.9

35d9c5de · discri 2 · 7 years ago
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0.8

0db47541 · Implemented fine time calibration: compile project · 8 years ago
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0.7

195dec69 · Updated readme and bump to 0.7 · 8 years ago
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0.6

ab493c3a · Compiled for data rate measurement · 8 years ago
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0.5

4d01b593 · Updated readme · 8 years ago
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0.4

344449d9 · Compiled code · 8 years ago
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0.3

b266e70d · Removed db from git index · 8 years ago
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0.2

11ade22a · Updated project files · 8 years ago
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0.1

8d810b73 · Included command X"04" · 8 years ago
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