Commit 0a4e842d authored by Colin González's avatar Colin González
Browse files

Patched code with a port know to work on the same CPU core

parent c3fd9424
......@@ -63,8 +63,8 @@ INCLUDES += -Isrc/
OPTIM = -O3
CFLAGS = -Wall -mlong-calls -ffunction-sections
CFLAGS += -fomit-frame-pointer -fno-strict-aliasing -fno-dwarf2-cfi-asm
CFLAGS = -Wall -Wextra
CFLAGS += -mcpu=arm926ej-s # -fomit-frame-pointer -fno-strict-aliasing -fno-dwarf2-cfi-asm
CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
CFLAGS += -g $(OPTIM) $(INCLUDES) -D$(CHIP)
# -DTRACE_LEVE=$(TRACE_LEVEL)
......
......@@ -8,11 +8,11 @@
#define configUSE_TICK_HOOK 0
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE ( (unsigned short) 128 )
#define configTOTAL_HEAP_SIZE ( (size_t) (42 * 1024) )
#define configTOTAL_HEAP_SIZE ( (size_t) (20480) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_APPLICATION_TASK_TAG 1
#define configUSE_CO_ROUTINES 0
......@@ -20,12 +20,27 @@
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* This is the raw value as per the Cortex-M3 NVIC. Values can be 255
(lowest) to 0 (1?) (highest). */
#define configKERNEL_INTERRUPT_PRIORITY 255
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xb0, or priority 11. */
/* This is the value being used as per the ST library which permits 16
priority values, 0 to 15. This must correspond to the
configKERNEL_INTERRUPT_PRIORITY setting. Here 15 corresponds to the lowest
NVIC value of 255. */
#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15
/* #define configYIELD_INTERRUPT_VECTOR 16UL */
/* #define configKERNEL_INTERRUPT_PRIORITY 1 */
/* #define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 */
......
......@@ -45,7 +45,7 @@
/*-----------------------------------------------------------*/
/* Constants required to setup the initial stack. */
#define portINITIAL_SPSR ((StackType_t) 0x1f)
#define portINITIAL_SPSR ((StackType_t) 0x5f)
/* System mode, ARM mode, interrupts enabled. */
#define portTHUMB_MODE_BIT ((StackType_t) 0x20)
#define portINSTRUCTION_SIZE ((StackType_t) 4)
......@@ -54,7 +54,7 @@
#define PIT_PERIOD 1000
/* Constants required to handle critical sections. */
#define portNO_CRITICAL_NESTING ((uint32_t)0)
#define portNO_CRITICAL_NESTING ((StackType_t) 0)
#define portINT_LEVEL_SENSITIVE 0
......
......@@ -22,7 +22,7 @@ void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
void vPortYieldProcessor (void){
__asm volatile ("ADD LR, LR,#4");
portSAVE_CONTEXT();
vTaskSwitchContext();
__asm volatile ( "bl vTaskSwitchContext" );
portRESTORE_CONTEXT();
}
......@@ -30,25 +30,17 @@ void vPortTickISR( void );
void vPortTickISR( void )
{
portSAVE_CONTEXT();
volatile uint32_t ulDummy;
volatile uint32_t status;
// Read the PIT status register
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
}
status = PIT_GetStatus() & AT91C_PITC_PITS;
if (status != 0) {
// 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
// Read the PIVR to acknowledge interrupt and get number of ticks
//Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
ulDummy += (PIT_GetPIVR() >> 20);
}
portRESTORE_CONTEXT();
/* Increment the tick count - which may wake some tasks but as the
preemptive scheduler is not being used any woken task is not given
processor time no matter what its priority. */
/* Clear the PIT interrupt. */
ulDummy = AT91C_BASE_PITC->PITC_PIVR;
/* To remove compiler warning. */
( void ) ulDummy;
}
/*-----------------------------------------------------------*/
......@@ -61,78 +53,83 @@ void vPortTickISR( void )
#ifdef THUMB_INTERWORK
void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
void vPortDisableInterruptsFromThumb( void )
{
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0x80\n"
"MSR CPSR, R0\n"
"ORR R0, R0, #0x40\n"
"MSR CPSR, R0 \n\t"
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
"BX R14" ); /* Return back to thumb. */
}
void vPortDisableInterruptsFromThumb( void )
{
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
"BX R14" ); /* Return back to thumb. */
}
void vPortEnableInterruptsFromThumb( void )
{
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
"BX R14" ); /* Return back to thumb. */
void vPortEnableInterruptsFromThumb( void )
{
/*
* NOTE:
* As FIQ is currently not supported, it is not enabled by the macro.
* If this is necessary, replace #0x80 by #0xC0.
*/
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0x80 \n\t" /* Enable IRQ. */
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
"BX R14" ); /* Return back to thumb. */
}
#endif
/* The code generated by the GCC compiler uses the stack in different ways at
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0x80\n"
"MSR CPSR, R0\n"
"ORR R0, R0, #0x40\n"
"MSR CPSR, R0 \n\t"
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
"BX R14" );
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
void vPortExitCritical( void )
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as we are leaving a critical section. */
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}" ); /* Pop R0. */
}
}
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as we are leaving a critical section. */
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/*
* NOTE:
* As FIQ is currently not supported, it is not enabled by the macro.
* If this is necessary, replace #0x80 by #0xC0.
*/
/* Enable interrupts as per portEXIT_CRITICAL(). */
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0x80 \n\t" /* Enable IRQ. */
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}" ); /* Pop R0. */
}
}
}
......@@ -45,17 +45,17 @@ extern "C" {
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG int32_t
#define portSHORT int16_t
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE portLong
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
typedef int32_t BaseType_t;
typedef uint32_t UBaseType_t;
#if( configUSE_16_BIT_TICKS == 1 )
......@@ -68,11 +68,10 @@ typedef unsigned long UBaseType_t;
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portYIELD() __asm volatile ( "SWI 0" )
#define portNOP() __asm volatile ( "NOP" )
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portNOP() __asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/
......@@ -87,107 +86,134 @@ typedef unsigned long UBaseType_t;
* THUMB mode code will result in a compile time error.
*/
#define portRESTORE_CONTEXT()\
{\
extern volatile void * volatile pxCurrentTCB;\
extern volatile uint32_t ulCriticalNesting;\
__asm volatile ( \
"LDR R1, =pxCurrentTCB\n"\
"LDR R0, [R1]\n"\
"LDR LR, [R0]\n"\
"LDR R0, =ulCriticalNesting\n"\
"LDMFD LR!, {R1}\n"\
"STR R1, [R0]\n"\
"LDMFD LR!, {R0}\n"\
"MSR SPSR_cxsf, R0\n"\
"LDMFD LR, {R0-R14}^\n"\
"NOP\n"\
"LDR LR, [LR, #+60]\n"\
"SUBS PC, LR, #4\n");\
(void) ulCriticalNesting; \
(void) pxCurrentTCB; \
}
#define portSAVE_CONTEXT() \
{\
extern volatile void * volatile pxCurrentTCB;\
extern volatile uint32_t ulCriticalNesting;\
__asm volatile ( \
"STMDB SP!, {R0}\n"\
"STMDB SP, {SP}^\n"\
"NOP\n"\
"SUB SP, SP, #4\n"\
"LDMIA SP!, {R0}\n"\
"STMDB R0!, {LR}\n"\
"MOV LR, R0\n"\
"LDMIA SP!, {R0}\n"\
"STMDB LR, {R0-LR}^\n"\
"NOP\n"\
"SUB LR, LR, #60\n"\
"MRS R0, SPSR\n"\
"STMDB LR!, {R0}\n"\
"LDR R0, =ulCriticalNesting\n"\
"LDR R0, [R0]\n"\
"STMDB LR!, {R0}\n"\
"LDR R1, =pxCurrentTCB\n"\
"LDR R0, [R1]\n"\
"STR LR, [R0]\n");\
(void) ulCriticalNesting; \
(void) pxCurrentTCB; \
}
#define portRESTORE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
__asm volatile ( \
"LDR R0, =pxCurrentTCB \n\t" \
"LDR R0, [R0] \n\t" \
"LDR LR, [R0] \n\t" \
\
/* The critical nesting depth is the first item on the stack. */ \
/* Load it into the ulCriticalNesting variable. */ \
"LDR R0, =ulCriticalNesting \n\t" \
"LDMFD LR!, {R1} \n\t" \
"STR R1, [R0] \n\t" \
\
/* Get the SPSR from the stack. */ \
"LDMFD LR!, {R0} \n\t" \
"MSR SPSR, R0 \n\t" \
\
/* Restore all system mode registers for the task. */ \
"LDMFD LR, {R0-R14}^ \n\t" \
"NOP \n\t" \
\
/* Restore the return address. */ \
"LDR LR, [LR, #+60] \n\t" \
\
/* And return - correcting the offset in the LR to obtain the */ \
/* correct address. */ \
"SUBS PC, LR, #4 \n\t" \
); \
( void ) ulCriticalNesting; \
( void ) pxCurrentTCB; \
}
/*-----------------------------------------------------------*/
#define portSAVE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" \
\
/* Set R0 to point to the task stack pointer. */ \
"STMDB SP,{SP}^ \n\t" \
"NOP \n\t" \
"SUB SP, SP, #4 \n\t" \
"LDMIA SP!,{R0} \n\t" \
\
/* Push the return address onto the stack. */ \
"STMDB R0!, {LR} \n\t" \
\
/* Now we have saved LR we can use it instead of R0. */ \
"MOV LR, R0 \n\t" \
\
/* Pop R0 so we can save it onto the system mode stack. */ \
"LDMIA SP!, {R0} \n\t" \
\
/* Push all the system mode registers onto the task stack. */ \
"STMDB LR,{R0-LR}^ \n\t" \
"NOP \n\t" \
"SUB LR, LR, #60 \n\t" \
\
/* Push the SPSR onto the task stack. */ \
"MRS R0, SPSR \n\t" \
"STMDB LR!, {R0} \n\t" \
\
"LDR R0, =ulCriticalNesting \n\t" \
"LDR R0, [R0] \n\t" \
"STMDB LR!, {R0} \n\t" \
\
/* Store the new top of stack for the task. */ \
"LDR R0, =pxCurrentTCB \n\t" \
"LDR R0, [R0] \n\t" \
"STR LR, [R0] \n\t" \
); \
( void ) ulCriticalNesting; \
( void ) pxCurrentTCB; \
}
extern void vTaskSwitchContext( void );
#define portYIELD_FROM_ISR() vTaskSwitchContext()
#define portYIELD() __asm volatile ( "SWI 0" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
#ifdef THUMB_INTERWORK
extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
#else
#define portDISABLE_INTERRUPTS()\
__asm volatile (\
"STMDB SP!, {R0}\n"\
"MRS R0, CPSR\n"\
"ORR R0, R0, #0x80\n"\
"MSR CPSR, R0\n"\
"ORR R0, R0, #0x40\n"\
"MSR CPSR, R0\n"
"LDMIA SP!, {R0}\n"\
"BX R14" )
#define portENABLE_INTERRUPTS()\
__asm volatile (\
"STMDB SP!, {R0}\n"\
"MRS R0, CPSR\n"\
"BIC R0, R0, #0xC0\n"\
"MSR CPSR, R0\n"\
"LDMIA SP!, {R0}\n")
#define portDISABLE_INTERRUPTS() \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
"LDMIA SP!, {R0} " ) /* Pop R0. */
/*
* NOTE:
* As FIQ is currently not supported, it is not enabled by the macro.
* If this is necessary, replace #0x80 by #0xC0.
*/
#define portENABLE_INTERRUPTS() \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"BIC R0, R0, #0x80 \n\t" /* Enable IRQ */ \
"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
"LDMIA SP!, {R0} " ) /* Pop R0. */
#endif
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern void vTaskSwitchContext( void ); \
\
if( xSwitchRequired ) \
{ \
vTaskSwitchContext(); \
} \
}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
......
#include <board.h>
#include <pio/pio.h>
#include <pio/pio_it.h>
#include <pit/pit.h>
#include <tc/tc.h>
#include <irq/irq.h>
#include <utility/led.h>
#include <utility/trace.h>
#include <stdio.h>
......@@ -8,34 +13,34 @@
/* type nom_de_fonction (type2 param1, type3 param2) { */
/* } */
typedef struct structure_struct {
int val1;
} structure_type;
/* typedef struct structure_struct { */
/* int val1; */
/* } structure_type; */
structure_type inc(structure_type x) {
structure_type a;
a.val1 = x.val1+1;
return a;
}
/* structure_type inc(structure_type x) { */
/* structure_type a; */
/* a.val1 = x.val1+1; */
/* return a; */
/* } */
int adds_one (int x) {
return x++;
}
/* int adds_one (int x) { */
/* return x++; */
/* } */
int times_two (int x) {
return (x * 2);
}
/* int times_two (int x) { */
/* return (x * 2); */
/* } */
int times_two_plus_one (int x){
return (adds_one(times_two(x)));
}
/* int times_two_plus_one (int x){ */
/* return (adds_one(times_two(x))); */
/* } */
int test_times_two (int input , int expected){
int x = times_two (input);
return (x == expected);
}
/* int test_times_two (int input , int expected){ */
/* int x = times_two (input); */
/* return (x == expected); */
/* } */
/* int many_test (void) { */
/* printf("many test"); */
......@@ -52,7 +57,6 @@ int test_times_two (int input , int expected){
/* return 1; */
/* } */
void task1(void *pParam) {
int i = 0;
......@@ -78,15 +82,13 @@ void ConfigureLeds (void) {
LED_Configure(1);
}
static void prvSetupHardware (void) {
AT91C_BASE_AIC->AIC_EOICR = 0;
ConfigureLeds();
}
/* static void prvSetupHardware (void) { */
/* AT91C_BASE_AIC->AIC_EOICR = 0; */
/* ConfigureLeds(); */
/* } */
int main () {
prvSetupHardware();
LED_Set(1);
/* TRACE_CONFIGURE(DBGU_STANDARD, 115200, BOARD_MCK); */
/* printf("-- Template project %s --\n\r", SOFTPACK_VERSION); */
/* printf("-- %s\n\r", BOARD_NAME); */
......@@ -94,9 +96,9 @@ int main () {
/* printf("--Testish\n\r"); */
/* int x = many_test(); */
/* printf("--Testouch %d \n\r", x); */
/* xTaskCreate(task1, "LED_0", 128, NULL, 0, NULL); */
/* xTaskCreate(task2, "LED_1", 128, NULL, 0, NULL); */