diff --git a/.gitignore b/.gitignore
index df92741a5457487dc89711fdc1c517b28104261f..8a3936cc7f614fd750c92027f21b9e97a6c9a7d8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,3 +7,4 @@
 sources/ip/data_bus/data_bus_clock_in/
 sources/ip/data_bus/data_bus_pio_0/
 sources/ip/data_bus/data_bus_reset_in/
+sources/data_bus/
diff --git a/scripts/set_project_files.tcl b/scripts/set_project_files.tcl
index 0bd0cbc23a019483236b78c965dc37c40aed2356..c57afde5264062699094eb0249858d9052a6cf54 100644
--- a/scripts/set_project_files.tcl
+++ b/scripts/set_project_files.tcl
@@ -5,7 +5,7 @@ set_global_assignment -name VERILOG_FILE $project_git/agilex_LL_firmware/sources
 
 
 set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_clock_in.ip
-set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_reset_i.ip
+set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_reset_in.ip
 set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_pio_0.ip
 
 set_global_assignment -name QSYS_FILE $project_git/agilex_LL_firmware/sources/data_bus.qsys