From 78a16c94d37b508ef1f8d1d2cf7bd2250496e3f0 Mon Sep 17 00:00:00 2001 From: Baptiste Lefevre <baptiste.lefevre@etu.emse.fr> Date: Wed, 7 Jul 2021 13:45:21 +0200 Subject: [PATCH] first ok compilation --- .gitignore | 1 + scripts/set_project_files.tcl | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index df92741..8a3936c 100644 --- a/.gitignore +++ b/.gitignore @@ -7,3 +7,4 @@ sources/ip/data_bus/data_bus_clock_in/ sources/ip/data_bus/data_bus_pio_0/ sources/ip/data_bus/data_bus_reset_in/ +sources/data_bus/ diff --git a/scripts/set_project_files.tcl b/scripts/set_project_files.tcl index 0bd0cbc..c57afde 100644 --- a/scripts/set_project_files.tcl +++ b/scripts/set_project_files.tcl @@ -5,7 +5,7 @@ set_global_assignment -name VERILOG_FILE $project_git/agilex_LL_firmware/sources set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_clock_in.ip -set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_reset_i.ip +set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_reset_in.ip set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_pio_0.ip set_global_assignment -name QSYS_FILE $project_git/agilex_LL_firmware/sources/data_bus.qsys -- GitLab