From 9ef095bdad7856ca1454f039a4ce40b59f65c35d Mon Sep 17 00:00:00 2001
From: Baptiste Lefevre <baptiste.lefevre@etu.emse.fr>
Date: Tue, 7 Sep 2021 14:51:12 +0200
Subject: [PATCH] keep only masters+pio ans the external reset
---
.gitignore | 3 +
agilex_LL_firmware.qsf | 4 -
source/agilex_LL_firmware.vhd | 160 +-
source/ip/pcie_ed/i2c_master_0.ip | 1145 -----
source/ip/pcie_ed/onchip_memory_0.ip | 1927 ---------
source/ip/pcie_ed/onchip_memory_1.ip | 1214 ------
source/ip/pcie_ed/pcie_ed_clock_bridge_0.ip | 343 --
source/pcie_ed.qsys | 4199 ++-----------------
8 files changed, 345 insertions(+), 8650 deletions(-)
delete mode 100644 source/ip/pcie_ed/i2c_master_0.ip
delete mode 100644 source/ip/pcie_ed/onchip_memory_0.ip
delete mode 100644 source/ip/pcie_ed/onchip_memory_1.ip
delete mode 100644 source/ip/pcie_ed/pcie_ed_clock_bridge_0.ip
diff --git a/.gitignore b/.gitignore
index c3b55b3..a80a43a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,6 +6,9 @@
output_files/
qdb/
tmp-clearbox/
+work/
+agilex_LL_firmware.qws
+
source/ip/pcie_ed/i2c_master_0/
source/ip/pcie_ed/jtag_master/
diff --git a/agilex_LL_firmware.qsf b/agilex_LL_firmware.qsf
index c473cba..ee253ec 100644
--- a/agilex_LL_firmware.qsf
+++ b/agilex_LL_firmware.qsf
@@ -141,13 +141,9 @@ set_global_assignment -name IP_FILE source/ip/pcie_ed/pcie_ed_DUT.ip
set_global_assignment -name QSYS_FILE source/pcie_ed.qsys
set_global_assignment -name IP_FILE source/ip/pcie_ed/pcie_ed_pio_0.ip
set_global_assignment -name IP_FILE source/ip/pcie_ed/jtag_master.ip
-set_global_assignment -name IP_FILE source/ip/pcie_ed/pcie_ed_clock_bridge_0.ip
set_global_assignment -name IP_FILE source/ip/pcie_ed/pcie_ed_reset_bridge_0.ip
set_global_assignment -name IP_FILE source/ip/pcie_ed/pcie_ed_pio_reset.ip
set_global_assignment -name IP_FILE source/ip/reset_release_ip.ip
-set_global_assignment -name IP_FILE source/ip/pcie_ed/onchip_memory_0.ip
-set_global_assignment -name IP_FILE source/ip/pcie_ed/onchip_memory_1.ip
-set_global_assignment -name IP_FILE source/ip/pcie_ed/i2c_master_0.ip
set_location_assignment PIN_F23 -to i2c_0_scl
diff --git a/source/agilex_LL_firmware.vhd b/source/agilex_LL_firmware.vhd
index 8deadc1..e12f96c 100644
--- a/source/agilex_LL_firmware.vhd
+++ b/source/agilex_LL_firmware.vhd
@@ -6,8 +6,8 @@ port(
--clk_sys_bak_50m_p : in std_logic;
--refclk_156m_qsfpdd_p : in std_logic;
clk_sys_100m_p : in std_logic;
- i2c_0_scl : inout std_logic;
- i2c_0_sda : inout std_logic;
+ --i2c_0_scl : inout std_logic;
+ --i2c_0_sda : inout std_logic;
refclk0_clk : in std_logic; -- refclk0.clk
refclk1_clk : in std_logic; -- refclk1.clk
@@ -88,82 +88,78 @@ end entity;
architecture rtl of agilex_LL_firmware is
- component pcie_ed is
+ component pcie_ed is
port (
- refclk0_clk : in std_logic := 'X'; -- clk
- refclk1_clk : in std_logic := 'X'; -- clk
- pin_perst_pin_perst : in std_logic := 'X'; -- pin_perst
- pcie_ninit_done_ninit_done : in std_logic := 'X'; -- ninit_done
- hip_serial_rx_n_in1 : in std_logic := 'X'; -- rx_n_in1
- hip_serial_tx_n_out8 : out std_logic; -- tx_n_out8
- hip_serial_rx_n_in2 : in std_logic := 'X'; -- rx_n_in2
- hip_serial_rx_p_in0 : in std_logic := 'X'; -- rx_p_in0
- hip_serial_rx_p_in15 : in std_logic := 'X'; -- rx_p_in15
- hip_serial_tx_p_out14 : out std_logic; -- tx_p_out14
- hip_serial_tx_p_out5 : out std_logic; -- tx_p_out5
- hip_serial_rx_p_in1 : in std_logic := 'X'; -- rx_p_in1
- hip_serial_tx_p_out15 : out std_logic; -- tx_p_out15
- hip_serial_rx_p_in4 : in std_logic := 'X'; -- rx_p_in4
- hip_serial_tx_n_out13 : out std_logic; -- tx_n_out13
- hip_serial_tx_p_out4 : out std_logic; -- tx_p_out4
- hip_serial_rx_n_in15 : in std_logic := 'X'; -- rx_n_in15
- hip_serial_tx_p_out10 : out std_logic; -- tx_p_out10
- hip_serial_rx_p_in3 : in std_logic := 'X'; -- rx_p_in3
- hip_serial_rx_n_in14 : in std_logic := 'X'; -- rx_n_in14
- hip_serial_tx_n_out14 : out std_logic; -- tx_n_out14
- hip_serial_tx_n_out0 : out std_logic; -- tx_n_out0
- hip_serial_tx_p_out13 : out std_logic; -- tx_p_out13
- hip_serial_tx_p_out7 : out std_logic; -- tx_p_out7
- hip_serial_tx_p_out1 : out std_logic; -- tx_p_out1
- hip_serial_rx_p_in7 : in std_logic := 'X'; -- rx_p_in7
- hip_serial_tx_n_out11 : out std_logic; -- tx_n_out11
- hip_serial_rx_n_in3 : in std_logic := 'X'; -- rx_n_in3
- hip_serial_tx_p_out11 : out std_logic; -- tx_p_out11
- hip_serial_rx_n_in4 : in std_logic := 'X'; -- rx_n_in4
- hip_serial_tx_p_out6 : out std_logic; -- tx_p_out6
- hip_serial_rx_n_in8 : in std_logic := 'X'; -- rx_n_in8
- hip_serial_tx_n_out3 : out std_logic; -- tx_n_out3
- hip_serial_rx_n_in5 : in std_logic := 'X'; -- rx_n_in5
- hip_serial_rx_n_in12 : in std_logic := 'X'; -- rx_n_in12
- hip_serial_rx_n_in6 : in std_logic := 'X'; -- rx_n_in6
- hip_serial_rx_n_in11 : in std_logic := 'X'; -- rx_n_in11
- hip_serial_rx_n_in9 : in std_logic := 'X'; -- rx_n_in9
- hip_serial_tx_n_out2 : out std_logic; -- tx_n_out2
- hip_serial_tx_n_out4 : out std_logic; -- tx_n_out4
- hip_serial_tx_p_out8 : out std_logic; -- tx_p_out8
- hip_serial_tx_n_out12 : out std_logic; -- tx_n_out12
- hip_serial_tx_n_out9 : out std_logic; -- tx_n_out9
- hip_serial_tx_p_out0 : out std_logic; -- tx_p_out0
- hip_serial_tx_n_out5 : out std_logic; -- tx_n_out5
- hip_serial_tx_p_out9 : out std_logic; -- tx_p_out9
- hip_serial_tx_n_out15 : out std_logic; -- tx_n_out15
- hip_serial_rx_p_in10 : in std_logic := 'X'; -- rx_p_in10
- hip_serial_rx_n_in13 : in std_logic := 'X'; -- rx_n_in13
- hip_serial_rx_p_in5 : in std_logic := 'X'; -- rx_p_in5
- hip_serial_tx_p_out3 : out std_logic; -- tx_p_out3
- hip_serial_rx_n_in7 : in std_logic := 'X'; -- rx_n_in7
- hip_serial_rx_p_in12 : in std_logic := 'X'; -- rx_p_in12
- hip_serial_tx_n_out6 : out std_logic; -- tx_n_out6
- hip_serial_rx_p_in13 : in std_logic := 'X'; -- rx_p_in13
- hip_serial_rx_p_in2 : in std_logic := 'X'; -- rx_p_in2
- hip_serial_tx_p_out2 : out std_logic; -- tx_p_out2
- hip_serial_rx_p_in8 : in std_logic := 'X'; -- rx_p_in8
- hip_serial_rx_p_in9 : in std_logic := 'X'; -- rx_p_in9
- hip_serial_tx_p_out12 : out std_logic; -- tx_p_out12
- hip_serial_rx_n_in10 : in std_logic := 'X'; -- rx_n_in10
- hip_serial_tx_n_out1 : out std_logic; -- tx_n_out1
- hip_serial_rx_p_in14 : in std_logic := 'X'; -- rx_p_in14
- hip_serial_tx_n_out7 : out std_logic; -- tx_n_out7
- hip_serial_tx_n_out10 : out std_logic; -- tx_n_out10
- hip_serial_rx_p_in6 : in std_logic := 'X'; -- rx_p_in6
- hip_serial_rx_n_in0 : in std_logic := 'X'; -- rx_n_in0
- hip_serial_rx_p_in11 : in std_logic := 'X'; -- rx_p_in11
- clock_100_in_clk_clk : in std_logic := 'X'; -- clk
- i2c_master_0_scl_sda_scl : inout std_logic := 'X'; -- scl
- i2c_master_0_scl_sda_sda : inout std_logic := 'X'; -- sda
- pio_out_port_export : out std_logic_vector(31 downto 0); -- export
- pio_reset_export : out std_logic; -- export
- bus_reset_in_reset : in std_logic := 'X' -- reset
+ refclk0_clk : in std_logic := 'X'; -- clk
+ refclk1_clk : in std_logic := 'X'; -- clk
+ pin_perst_pin_perst : in std_logic := 'X'; -- pin_perst
+ pcie_ninit_done_ninit_done : in std_logic := 'X'; -- ninit_done
+ hip_serial_rx_n_in1 : in std_logic := 'X'; -- rx_n_in1
+ hip_serial_tx_n_out8 : out std_logic; -- tx_n_out8
+ hip_serial_rx_n_in2 : in std_logic := 'X'; -- rx_n_in2
+ hip_serial_rx_p_in0 : in std_logic := 'X'; -- rx_p_in0
+ hip_serial_rx_p_in15 : in std_logic := 'X'; -- rx_p_in15
+ hip_serial_tx_p_out14 : out std_logic; -- tx_p_out14
+ hip_serial_tx_p_out5 : out std_logic; -- tx_p_out5
+ hip_serial_rx_p_in1 : in std_logic := 'X'; -- rx_p_in1
+ hip_serial_tx_p_out15 : out std_logic; -- tx_p_out15
+ hip_serial_rx_p_in4 : in std_logic := 'X'; -- rx_p_in4
+ hip_serial_tx_n_out13 : out std_logic; -- tx_n_out13
+ hip_serial_tx_p_out4 : out std_logic; -- tx_p_out4
+ hip_serial_rx_n_in15 : in std_logic := 'X'; -- rx_n_in15
+ hip_serial_tx_p_out10 : out std_logic; -- tx_p_out10
+ hip_serial_rx_p_in3 : in std_logic := 'X'; -- rx_p_in3
+ hip_serial_rx_n_in14 : in std_logic := 'X'; -- rx_n_in14
+ hip_serial_tx_n_out14 : out std_logic; -- tx_n_out14
+ hip_serial_tx_n_out0 : out std_logic; -- tx_n_out0
+ hip_serial_tx_p_out13 : out std_logic; -- tx_p_out13
+ hip_serial_tx_p_out7 : out std_logic; -- tx_p_out7
+ hip_serial_tx_p_out1 : out std_logic; -- tx_p_out1
+ hip_serial_rx_p_in7 : in std_logic := 'X'; -- rx_p_in7
+ hip_serial_tx_n_out11 : out std_logic; -- tx_n_out11
+ hip_serial_rx_n_in3 : in std_logic := 'X'; -- rx_n_in3
+ hip_serial_tx_p_out11 : out std_logic; -- tx_p_out11
+ hip_serial_rx_n_in4 : in std_logic := 'X'; -- rx_n_in4
+ hip_serial_tx_p_out6 : out std_logic; -- tx_p_out6
+ hip_serial_rx_n_in8 : in std_logic := 'X'; -- rx_n_in8
+ hip_serial_tx_n_out3 : out std_logic; -- tx_n_out3
+ hip_serial_rx_n_in5 : in std_logic := 'X'; -- rx_n_in5
+ hip_serial_rx_n_in12 : in std_logic := 'X'; -- rx_n_in12
+ hip_serial_rx_n_in6 : in std_logic := 'X'; -- rx_n_in6
+ hip_serial_rx_n_in11 : in std_logic := 'X'; -- rx_n_in11
+ hip_serial_rx_n_in9 : in std_logic := 'X'; -- rx_n_in9
+ hip_serial_tx_n_out2 : out std_logic; -- tx_n_out2
+ hip_serial_tx_n_out4 : out std_logic; -- tx_n_out4
+ hip_serial_tx_p_out8 : out std_logic; -- tx_p_out8
+ hip_serial_tx_n_out12 : out std_logic; -- tx_n_out12
+ hip_serial_tx_n_out9 : out std_logic; -- tx_n_out9
+ hip_serial_tx_p_out0 : out std_logic; -- tx_p_out0
+ hip_serial_tx_n_out5 : out std_logic; -- tx_n_out5
+ hip_serial_tx_p_out9 : out std_logic; -- tx_p_out9
+ hip_serial_tx_n_out15 : out std_logic; -- tx_n_out15
+ hip_serial_rx_p_in10 : in std_logic := 'X'; -- rx_p_in10
+ hip_serial_rx_n_in13 : in std_logic := 'X'; -- rx_n_in13
+ hip_serial_rx_p_in5 : in std_logic := 'X'; -- rx_p_in5
+ hip_serial_tx_p_out3 : out std_logic; -- tx_p_out3
+ hip_serial_rx_n_in7 : in std_logic := 'X'; -- rx_n_in7
+ hip_serial_rx_p_in12 : in std_logic := 'X'; -- rx_p_in12
+ hip_serial_tx_n_out6 : out std_logic; -- tx_n_out6
+ hip_serial_rx_p_in13 : in std_logic := 'X'; -- rx_p_in13
+ hip_serial_rx_p_in2 : in std_logic := 'X'; -- rx_p_in2
+ hip_serial_tx_p_out2 : out std_logic; -- tx_p_out2
+ hip_serial_rx_p_in8 : in std_logic := 'X'; -- rx_p_in8
+ hip_serial_rx_p_in9 : in std_logic := 'X'; -- rx_p_in9
+ hip_serial_tx_p_out12 : out std_logic; -- tx_p_out12
+ hip_serial_rx_n_in10 : in std_logic := 'X'; -- rx_n_in10
+ hip_serial_tx_n_out1 : out std_logic; -- tx_n_out1
+ hip_serial_rx_p_in14 : in std_logic := 'X'; -- rx_p_in14
+ hip_serial_tx_n_out7 : out std_logic; -- tx_n_out7
+ hip_serial_tx_n_out10 : out std_logic; -- tx_n_out10
+ hip_serial_rx_p_in6 : in std_logic := 'X'; -- rx_p_in6
+ hip_serial_rx_n_in0 : in std_logic := 'X'; -- rx_n_in0
+ hip_serial_rx_p_in11 : in std_logic := 'X'; -- rx_p_in11
+ pio_out_port_export : out std_logic_vector(31 downto 0); -- export
+ bus_reset_in_reset : in std_logic := 'X' -- reset
);
end component pcie_ed;
@@ -197,7 +193,7 @@ signal bus_reset_s : std_logic;
bus_reset_ip : component reset_state_machine
port map(
clk_i => clk_sys_100m_p,
- enable_i => pio_reset_output_s,
+ enable_i => '0', --pio_reset_output_s,
reset_o => bus_reset_s
);
@@ -271,11 +267,11 @@ signal bus_reset_s : std_logic;
hip_serial_rx_p_in6 => pcie_rx_p_in6, -- .rx_p_in6
hip_serial_rx_n_in0 => pcie_rx_n_in0, -- .rx_n_in0
hip_serial_rx_p_in11 => pcie_rx_p_in11, -- .rx_p_in11
- clock_100_in_clk_clk => clk_sys_100m_p, -- clock_100_in_clk.clk
- i2c_master_0_scl_sda_scl => i2c_0_scl, -- scl
- i2c_master_0_scl_sda_sda => i2c_0_sda,
+ --clock_100_in_clk_clk => clk_sys_100m_p, -- clock_100_in_clk.clk
+ --i2c_master_0_scl_sda_scl => i2c_0_scl, -- scl
+ --i2c_master_0_scl_sda_sda => i2c_0_sda,
pio_out_port_export => pio_out0, -- pio_out_port.export
- pio_reset_export => pio_reset_output_s,
+ --pio_reset_export => pio_reset_output_s,
bus_reset_in_reset => bus_reset_s -- 1 means reset
);
diff --git a/source/ip/pcie_ed/i2c_master_0.ip b/source/ip/pcie_ed/i2c_master_0.ip
deleted file mode 100644
index 7c8c992..0000000
--- a/source/ip/pcie_ed/i2c_master_0.ip
+++ /dev/null
@@ -1,1145 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>Altera Corporation</ipxact:vendor>
- <ipxact:library>i2c_master_0</ipxact:library>
- <ipxact:name>i2c_master_0</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_clk_i</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>clk_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_rst_i</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>avalon_i2c_slave</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_adr_i</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_dat_i</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_dat_o</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_we_i</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>chipselect</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_stb_i</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>waitrequest_n</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_ack_o</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Agent addressing</ipxact:displayName>
- <ipxact:value>NATIVE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>clk_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to host</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>irq</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="interrupt" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="interrupt" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>irq</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>wb_inta_o</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedAddressablePoint" type="string">
- <ipxact:name>associatedAddressablePoint</ipxact:name>
- <ipxact:displayName>Associated addressable interface</ipxact:displayName>
- <ipxact:value>i2c_master_0.avalon_i2c_slave</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>clk_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedReceiverOffset" type="longint">
- <ipxact:name>bridgedReceiverOffset</ipxact:name>
- <ipxact:displayName>Bridged receiver offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToReceiver" type="string">
- <ipxact:name>bridgesToReceiver</ipxact:name>
- <ipxact:displayName>Bridges to receiver</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="irqScheme" type="string">
- <ipxact:name>irqScheme</ipxact:name>
- <ipxact:displayName>Interrupt scheme</ipxact:displayName>
- <ipxact:value>NONE</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>scl_sda</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>scl</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>scl_pad_io</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>sda</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>sda_pad_io</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>opencores_i2c</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>wb_clk_i</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_rst_i</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_adr_i</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>2</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_dat_i</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>7</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_dat_o</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>7</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_we_i</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_stb_i</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_ack_o</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>wb_inta_o</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>scl_pad_io</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>inout</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>sda_pad_io</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>inout</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>Altera Corporation</ipxact:vendor>
- <ipxact:library>i2c_master_0</ipxact:library>
- <ipxact:name>opencores_i2c</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters></ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>AGFB014R24A2E2VR0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Agilex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_clk_i</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_rst_i</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>avalon_i2c_slave</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_adr_i</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_dat_i</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_dat_o</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_we_i</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_stb_i</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_ack_o</name>
- <role>waitrequest_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_inta_o</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>i2c_master_0.avalon_i2c_slave</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>scl_sda</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>scl_pad_io</name>
- <role>scl</role>
- <direction>Bidir</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>sda_pad_io</name>
- <role>sda</role>
- <direction>Bidir</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>avalon_i2c_slave</key>
- <value>
- <connectionPointName>avalon_i2c_slave</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='avalon_i2c_slave' start='0x0' end='0x20' datawidth='8' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>5</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>8</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="avalon_i2c_slave" altera:internal="i2c_master_0.avalon_i2c_slave" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="wb_ack_o" altera:internal="wb_ack_o"></altera:port_mapping>
- <altera:port_mapping altera:name="wb_adr_i" altera:internal="wb_adr_i"></altera:port_mapping>
- <altera:port_mapping altera:name="wb_dat_i" altera:internal="wb_dat_i"></altera:port_mapping>
- <altera:port_mapping altera:name="wb_dat_o" altera:internal="wb_dat_o"></altera:port_mapping>
- <altera:port_mapping altera:name="wb_stb_i" altera:internal="wb_stb_i"></altera:port_mapping>
- <altera:port_mapping altera:name="wb_we_i" altera:internal="wb_we_i"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="i2c_master_0.clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="wb_clk_i" altera:internal="wb_clk_i"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk_reset" altera:internal="i2c_master_0.clk_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="wb_rst_i" altera:internal="wb_rst_i"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="irq" altera:internal="i2c_master_0.irq" altera:type="interrupt" altera:dir="end">
- <altera:port_mapping altera:name="wb_inta_o" altera:internal="wb_inta_o"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="scl_sda" altera:internal="i2c_master_0.scl_sda" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="scl_pad_io" altera:internal="scl_pad_io"></altera:port_mapping>
- <altera:port_mapping altera:name="sda_pad_io" altera:internal="sda_pad_io"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/source/ip/pcie_ed/onchip_memory_0.ip b/source/ip/pcie_ed/onchip_memory_0.ip
deleted file mode 100644
index 28a4021..0000000
--- a/source/ip/pcie_ed/onchip_memory_0.ip
+++ /dev/null
@@ -1,1927 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>onchip_memory_0</ipxact:library>
- <ipxact:name>onchip_memory_0</ipxact:name>
- <ipxact:version>19.3.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>clk1</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>s1</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clken</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>clken</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>chipselect</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>chipselect</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>byteenable</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>byteenable</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Agent addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>reset1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to host</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset1</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset_req</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>reset_req</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>s2</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>address2</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>chipselect</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>chipselect2</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clken</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>clken2</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>write2</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>readdata2</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>writedata2</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>byteenable</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>byteenable2</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Agent addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>reset1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to host</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>altera_avalon_onchip_memory2</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>9</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>clken</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>chipselect</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>byteenable</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>3</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>reset_req</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>address2</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>9</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>chipselect2</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>clken2</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>write2</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>readdata2</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>writedata2</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>byteenable2</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>3</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>onchip_memory_0</ipxact:library>
- <ipxact:name>altera_avalon_onchip_memory2</ipxact:name>
- <ipxact:version>19.3.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="allowInSystemMemoryContentEditor" type="bit">
- <ipxact:name>allowInSystemMemoryContentEditor</ipxact:name>
- <ipxact:displayName>Enable In-System Memory Content Editor feature</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="blockType" type="string">
- <ipxact:name>blockType</ipxact:name>
- <ipxact:displayName>Block type</ipxact:displayName>
- <ipxact:value>AUTO</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="dataWidth" type="int">
- <ipxact:name>dataWidth</ipxact:name>
- <ipxact:displayName>Slave S1 Data width</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="dataWidth2" type="int">
- <ipxact:name>dataWidth2</ipxact:name>
- <ipxact:displayName>Slave S2 Data width</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="dualPort" type="bit">
- <ipxact:name>dualPort</ipxact:name>
- <ipxact:displayName>Dual-port access</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="enableDiffWidth" type="bit">
- <ipxact:name>enableDiffWidth</ipxact:name>
- <ipxact:displayName>Enable different width for Dual-port access</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="initMemContent" type="bit">
- <ipxact:name>initMemContent</ipxact:name>
- <ipxact:displayName>Initialize memory content</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="initializationFileName" type="string">
- <ipxact:name>initializationFileName</ipxact:name>
- <ipxact:displayName>User created initialization file</ipxact:displayName>
- <ipxact:value>onchip_mem.hex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="enPRInitMode" type="bit">
- <ipxact:name>enPRInitMode</ipxact:name>
- <ipxact:displayName>Enable Partial Reconfiguration Initialization Mode</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="instanceID" type="string">
- <ipxact:name>instanceID</ipxact:name>
- <ipxact:displayName>Instance ID</ipxact:displayName>
- <ipxact:value>NONE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="memorySize" type="longint">
- <ipxact:name>memorySize</ipxact:name>
- <ipxact:displayName>Total memory size</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readDuringWriteMode" type="string">
- <ipxact:name>readDuringWriteMode</ipxact:name>
- <ipxact:displayName>Read During Write Mode</ipxact:displayName>
- <ipxact:value>DONT_CARE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="simAllowMRAMContentsFile" type="bit">
- <ipxact:name>simAllowMRAMContentsFile</ipxact:name>
- <ipxact:displayName>Allow MRAM contents file for simulation</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="simMemInitOnlyFilename" type="int">
- <ipxact:name>simMemInitOnlyFilename</ipxact:name>
- <ipxact:displayName>Simulation meminit only has filename</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="singleClockOperation" type="bit">
- <ipxact:name>singleClockOperation</ipxact:name>
- <ipxact:displayName>Single clock operation</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="slave1Latency" type="int">
- <ipxact:name>slave1Latency</ipxact:name>
- <ipxact:displayName>Slave s1 Latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="slave2Latency" type="int">
- <ipxact:name>slave2Latency</ipxact:name>
- <ipxact:displayName>Slave s2 Latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="useNonDefaultInitFile" type="bit">
- <ipxact:name>useNonDefaultInitFile</ipxact:name>
- <ipxact:displayName>Enable non-default initialization file</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="copyInitFile" type="bit">
- <ipxact:name>copyInitFile</ipxact:name>
- <ipxact:displayName> Copy non-default initialization file to generated folder</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="useShallowMemBlocks" type="bit">
- <ipxact:name>useShallowMemBlocks</ipxact:name>
- <ipxact:displayName>Minimize memory block usage (may impact fmax)</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writable" type="bit">
- <ipxact:name>writable</ipxact:name>
- <ipxact:displayName>Type</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ecc_enabled" type="bit">
- <ipxact:name>ecc_enabled</ipxact:name>
- <ipxact:displayName>Extend the data width to support ECC bits</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="resetrequest_enabled" type="bit">
- <ipxact:name>resetrequest_enabled</ipxact:name>
- <ipxact:displayName>Reset Request</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="autoInitializationFileName" type="string">
- <ipxact:name>autoInitializationFileName</ipxact:name>
- <ipxact:displayName>autoInitializationFileName</ipxact:displayName>
- <ipxact:value>onchip_memory_0_onchip_memory_0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>deviceFamily</ipxact:displayName>
- <ipxact:value>Agilex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFeatures" type="string">
- <ipxact:name>deviceFeatures</ipxact:name>
- <ipxact:displayName>deviceFeatures</ipxact:displayName>
- <ipxact:value>ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ALLOW_NO_JTAG_ID 0 ANY_QFP 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 BLACKLISTS_HIERARCHIES 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 CORRELATED_TIMING_MODEL 0 DISABLE_COMPILER_SUPPORT 0 DISABLE_CRC_ERROR_DETECTION 0 DISABLE_DUAL_BOOT 0 DISABLE_ERAM_PRELOAD 0 DOES_NOT_HAVE_DPA_SILICON_FIX_IN_ENGINEERING_SAMPLE 0 DOES_NOT_SUPPORT_TIMING_MODELS_FOR_ROUTING_WIRES_WITH_ONLY_REDUNDANT_FANOUTS 0 DSP 1 DUMP_ASM_LAB_BITS_FOR_POWER 0 ECCN_3A991 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FAST_POWER_ON_RESET 0 FINAL_DEVICE_MODEL 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FM_REVB 0 FORBID_MIGRATION_ES_WITH_PRODUCTION 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HARDCOPY_PROTOTYPE 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 0 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CROSS_FEATURE_VERTICAL_MIGRATION_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 0 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_DIB 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_EPEQ_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FAST_PRESERVATION_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 0 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 0 HAS_HARDCOPYII_SUPPORT 0 HAS_HARDCOPY_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LAB_LATCHES 1 HAS_LEIM_RES_MERGED_IN_RR_GRAPH 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 0 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MISSING_PKG_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 1 HAS_NADDER_STYLE_FF 1 HAS_NADDER_STYLE_LCELL_COMB 1 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_DATA_DRIVEN_PACKAGE_INFO 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRELIMINARY_HSSI_TO_PLD_MCF_CONNECTIVITY 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 0 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QSPI_RESET_SUPPORT 0 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 1 HAS_SPEED_GRADE_OFFSET 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 0 HAS_VIRTUAL_DEVICES 0 HAS_VOLTAGE_REGULATOR 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 1 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_STATIC_PART 0 INTERNAL_USE_ONLY 0 IN_BRINGUP 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_32_BIT_QUARTUS_COMPATIBLE 0 IS_ALTERA_QSPI_DEVICE 0 IS_ASC_DEVICE 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOWER_POWER 0 IS_LOW_POWER_PART 0 IS_MCP_DEVICE 0 IS_QSPI_DEVICE 0 IS_REVE_SILICON 0 IS_SC_DEVICE 0 IS_SDM_LITE 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 IS_TSUNAMI_VER 0 IS_UDM_BASED 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 1 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M20K_MEMORY 1 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 NOT_AUTOSELECTED 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NOT_SUPPORTED_BY_QPA 0 NO_CLOCK_REGION 0 NO_DATA_FILES 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PINTABLE_AND_FULLCHIP_SUPPORT 0 NO_PIN_OUT 0 NO_POF 0 NO_ROUTING 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PRE_ND5_L_FINALITY 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 QPA_USES_PAN2 1 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRES_TLG 0 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 1 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_ADVANCED_SECURITY 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_EASIC 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 1 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_PARTIAL_MIGRATION 0 SUPPORTS_PSEUDO_LATCHES_ONLY 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORTS_VID_ALGORITHM 1 SUPPORT_HBM_IN_EPE 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_MULTIPLE_PAD_PER_PIN 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DMF_TIMING 0 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_FAMILY_PART_INFO 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_ANNOTATION_FOR_LAB_OUTPUTS 1 USES_LIBERTY_ANNOTATION_FOR_M20K_DSP_OUTPUTS 1 USES_LIBERTY_TIMING 0 USES_MULTIPLE_VID_VOLTAGES 0 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_SPECIFIC_DEV_FILES 0 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USES_TIMING_ROUTING_DELAYS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USE_VIRTUAL_DEV_NAME_FOR_FDI 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 VERMEER_USES_TSUNAMI_DIE 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR" type="string">
- <ipxact:name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE" type="string">
- <ipxact:name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.CONTENTS_INFO" type="string">
- <ipxact:name>embeddedsw.CMacro.CONTENTS_INFO</ipxact:name>
- <ipxact:value>""</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.DUAL_PORT" type="string">
- <ipxact:name>embeddedsw.CMacro.DUAL_PORT</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE" type="string">
- <ipxact:name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</ipxact:name>
- <ipxact:value>AUTO</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.INIT_CONTENTS_FILE" type="string">
- <ipxact:name>embeddedsw.CMacro.INIT_CONTENTS_FILE</ipxact:name>
- <ipxact:value>onchip_memory_0_onchip_memory_0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.INIT_MEM_CONTENT" type="string">
- <ipxact:name>embeddedsw.CMacro.INIT_MEM_CONTENT</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.INSTANCE_ID" type="string">
- <ipxact:name>embeddedsw.CMacro.INSTANCE_ID</ipxact:name>
- <ipxact:value>NONE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED" type="string">
- <ipxact:name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.RAM_BLOCK_TYPE" type="string">
- <ipxact:name>embeddedsw.CMacro.RAM_BLOCK_TYPE</ipxact:name>
- <ipxact:value>AUTO</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.READ_DURING_WRITE_MODE" type="string">
- <ipxact:name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</ipxact:name>
- <ipxact:value>DONT_CARE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.SINGLE_CLOCK_OP" type="string">
- <ipxact:name>embeddedsw.CMacro.SINGLE_CLOCK_OP</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.SIZE_MULTIPLE" type="string">
- <ipxact:name>embeddedsw.CMacro.SIZE_MULTIPLE</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.SIZE_VALUE" type="string">
- <ipxact:name>embeddedsw.CMacro.SIZE_VALUE</ipxact:name>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.WRITABLE" type="string">
- <ipxact:name>embeddedsw.CMacro.WRITABLE</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR" type="string">
- <ipxact:name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</ipxact:name>
- <ipxact:value>SIM_DIR</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.GENERATE_DAT_SYM" type="string">
- <ipxact:name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.GENERATE_HEX" type="string">
- <ipxact:name>embeddedsw.memoryInfo.GENERATE_HEX</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.HAS_BYTE_LANE" type="string">
- <ipxact:name>embeddedsw.memoryInfo.HAS_BYTE_LANE</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.HEX_INSTALL_DIR" type="string">
- <ipxact:name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</ipxact:name>
- <ipxact:value>QPF_DIR</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH" type="string">
- <ipxact:name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</ipxact:name>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.MEM_INIT_FILENAME" type="string">
- <ipxact:name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</ipxact:name>
- <ipxact:value>onchip_memory_0_onchip_memory_0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="postgeneration.simulation.init_file.param_name" type="string">
- <ipxact:name>postgeneration.simulation.init_file.param_name</ipxact:name>
- <ipxact:value>INIT_FILE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="postgeneration.simulation.init_file.type" type="string">
- <ipxact:name>postgeneration.simulation.init_file.type</ipxact:name>
- <ipxact:value>MEM_INIT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>AGFB014R24A2E2VR0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Agilex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Agilex";
- type = "String";
- }
- }
- element onchip_memory_0
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s2</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address2</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>chipselect2</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>clken2</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>write2</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>readdata2</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>writedata2</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>byteenable2</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>s1</key>
- <value>
- <connectionPointName>s1</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>s2</key>
- <value>
- <connectionPointName>s2</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='s2' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="clk1" altera:internal="onchip_memory_0.clk1" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset1" altera:internal="onchip_memory_0.reset1" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="reset" altera:internal="reset"></altera:port_mapping>
- <altera:port_mapping altera:name="reset_req" altera:internal="reset_req"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="s1" altera:internal="onchip_memory_0.s1" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping>
- <altera:port_mapping altera:name="byteenable" altera:internal="byteenable"></altera:port_mapping>
- <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping>
- <altera:port_mapping altera:name="clken" altera:internal="clken"></altera:port_mapping>
- <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="write" altera:internal="write"></altera:port_mapping>
- <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="s2" altera:internal="onchip_memory_0.s2" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="address2" altera:internal="address2"></altera:port_mapping>
- <altera:port_mapping altera:name="byteenable2" altera:internal="byteenable2"></altera:port_mapping>
- <altera:port_mapping altera:name="chipselect2" altera:internal="chipselect2"></altera:port_mapping>
- <altera:port_mapping altera:name="clken2" altera:internal="clken2"></altera:port_mapping>
- <altera:port_mapping altera:name="readdata2" altera:internal="readdata2"></altera:port_mapping>
- <altera:port_mapping altera:name="write2" altera:internal="write2"></altera:port_mapping>
- <altera:port_mapping altera:name="writedata2" altera:internal="writedata2"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/source/ip/pcie_ed/onchip_memory_1.ip b/source/ip/pcie_ed/onchip_memory_1.ip
deleted file mode 100644
index 1e15a0e..0000000
--- a/source/ip/pcie_ed/onchip_memory_1.ip
+++ /dev/null
@@ -1,1214 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>onchip_memory_1</ipxact:library>
- <ipxact:name>onchip_memory_1</ipxact:name>
- <ipxact:version>19.3.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>clk1</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>s1</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clken</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>clken</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>chipselect</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>chipselect</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>byteenable</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>byteenable</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Agent addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>reset1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to host</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset1</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset_req</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>reset_req</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>clk1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>altera_avalon_onchip_memory2</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>9</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>clken</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>chipselect</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>byteenable</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>3</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>reset_req</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>onchip_memory_1</ipxact:library>
- <ipxact:name>altera_avalon_onchip_memory2</ipxact:name>
- <ipxact:version>19.3.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="allowInSystemMemoryContentEditor" type="bit">
- <ipxact:name>allowInSystemMemoryContentEditor</ipxact:name>
- <ipxact:displayName>Enable In-System Memory Content Editor feature</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="blockType" type="string">
- <ipxact:name>blockType</ipxact:name>
- <ipxact:displayName>Block type</ipxact:displayName>
- <ipxact:value>AUTO</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="dataWidth" type="int">
- <ipxact:name>dataWidth</ipxact:name>
- <ipxact:displayName>Slave S1 Data width</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="dataWidth2" type="int">
- <ipxact:name>dataWidth2</ipxact:name>
- <ipxact:displayName>Slave S2 Data width</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="dualPort" type="bit">
- <ipxact:name>dualPort</ipxact:name>
- <ipxact:displayName>Dual-port access</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="enableDiffWidth" type="bit">
- <ipxact:name>enableDiffWidth</ipxact:name>
- <ipxact:displayName>Enable different width for Dual-port access</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="initMemContent" type="bit">
- <ipxact:name>initMemContent</ipxact:name>
- <ipxact:displayName>Initialize memory content</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="initializationFileName" type="string">
- <ipxact:name>initializationFileName</ipxact:name>
- <ipxact:displayName>User created initialization file</ipxact:displayName>
- <ipxact:value>onchip_mem.hex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="enPRInitMode" type="bit">
- <ipxact:name>enPRInitMode</ipxact:name>
- <ipxact:displayName>Enable Partial Reconfiguration Initialization Mode</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="instanceID" type="string">
- <ipxact:name>instanceID</ipxact:name>
- <ipxact:displayName>Instance ID</ipxact:displayName>
- <ipxact:value>NONE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="memorySize" type="longint">
- <ipxact:name>memorySize</ipxact:name>
- <ipxact:displayName>Total memory size</ipxact:displayName>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readDuringWriteMode" type="string">
- <ipxact:name>readDuringWriteMode</ipxact:name>
- <ipxact:displayName>Read During Write Mode</ipxact:displayName>
- <ipxact:value>DONT_CARE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="simAllowMRAMContentsFile" type="bit">
- <ipxact:name>simAllowMRAMContentsFile</ipxact:name>
- <ipxact:displayName>Allow MRAM contents file for simulation</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="simMemInitOnlyFilename" type="int">
- <ipxact:name>simMemInitOnlyFilename</ipxact:name>
- <ipxact:displayName>Simulation meminit only has filename</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="singleClockOperation" type="bit">
- <ipxact:name>singleClockOperation</ipxact:name>
- <ipxact:displayName>Single clock operation</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="slave1Latency" type="int">
- <ipxact:name>slave1Latency</ipxact:name>
- <ipxact:displayName>Slave s1 Latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="slave2Latency" type="int">
- <ipxact:name>slave2Latency</ipxact:name>
- <ipxact:displayName>Slave s2 Latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="useNonDefaultInitFile" type="bit">
- <ipxact:name>useNonDefaultInitFile</ipxact:name>
- <ipxact:displayName>Enable non-default initialization file</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="copyInitFile" type="bit">
- <ipxact:name>copyInitFile</ipxact:name>
- <ipxact:displayName> Copy non-default initialization file to generated folder</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="useShallowMemBlocks" type="bit">
- <ipxact:name>useShallowMemBlocks</ipxact:name>
- <ipxact:displayName>Minimize memory block usage (may impact fmax)</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writable" type="bit">
- <ipxact:name>writable</ipxact:name>
- <ipxact:displayName>Type</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ecc_enabled" type="bit">
- <ipxact:name>ecc_enabled</ipxact:name>
- <ipxact:displayName>Extend the data width to support ECC bits</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="resetrequest_enabled" type="bit">
- <ipxact:name>resetrequest_enabled</ipxact:name>
- <ipxact:displayName>Reset Request</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="autoInitializationFileName" type="string">
- <ipxact:name>autoInitializationFileName</ipxact:name>
- <ipxact:displayName>autoInitializationFileName</ipxact:displayName>
- <ipxact:value>onchip_memory_1_onchip_memory_1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>deviceFamily</ipxact:displayName>
- <ipxact:value>Agilex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFeatures" type="string">
- <ipxact:name>deviceFeatures</ipxact:name>
- <ipxact:displayName>deviceFeatures</ipxact:displayName>
- <ipxact:value>ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ALLOW_NO_JTAG_ID 0 ANY_QFP 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 BLACKLISTS_HIERARCHIES 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 CORRELATED_TIMING_MODEL 0 DISABLE_COMPILER_SUPPORT 0 DISABLE_CRC_ERROR_DETECTION 0 DISABLE_DUAL_BOOT 0 DISABLE_ERAM_PRELOAD 0 DOES_NOT_HAVE_DPA_SILICON_FIX_IN_ENGINEERING_SAMPLE 0 DOES_NOT_SUPPORT_TIMING_MODELS_FOR_ROUTING_WIRES_WITH_ONLY_REDUNDANT_FANOUTS 0 DSP 1 DUMP_ASM_LAB_BITS_FOR_POWER 0 ECCN_3A991 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FAST_POWER_ON_RESET 0 FINAL_DEVICE_MODEL 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FM_REVB 0 FORBID_MIGRATION_ES_WITH_PRODUCTION 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HARDCOPY_PROTOTYPE 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 0 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CROSS_FEATURE_VERTICAL_MIGRATION_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 0 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_DIB 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_EPEQ_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FAST_PRESERVATION_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 0 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 0 HAS_HARDCOPYII_SUPPORT 0 HAS_HARDCOPY_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LAB_LATCHES 1 HAS_LEIM_RES_MERGED_IN_RR_GRAPH 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 0 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MISSING_PKG_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 1 HAS_NADDER_STYLE_FF 1 HAS_NADDER_STYLE_LCELL_COMB 1 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_DATA_DRIVEN_PACKAGE_INFO 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRELIMINARY_HSSI_TO_PLD_MCF_CONNECTIVITY 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 0 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QSPI_RESET_SUPPORT 0 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 1 HAS_SPEED_GRADE_OFFSET 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 0 HAS_VIRTUAL_DEVICES 0 HAS_VOLTAGE_REGULATOR 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 1 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_STATIC_PART 0 INTERNAL_USE_ONLY 0 IN_BRINGUP 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_32_BIT_QUARTUS_COMPATIBLE 0 IS_ALTERA_QSPI_DEVICE 0 IS_ASC_DEVICE 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOWER_POWER 0 IS_LOW_POWER_PART 0 IS_MCP_DEVICE 0 IS_QSPI_DEVICE 0 IS_REVE_SILICON 0 IS_SC_DEVICE 0 IS_SDM_LITE 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 IS_TSUNAMI_VER 0 IS_UDM_BASED 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 1 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M20K_MEMORY 1 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 NOT_AUTOSELECTED 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NOT_SUPPORTED_BY_QPA 0 NO_CLOCK_REGION 0 NO_DATA_FILES 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PINTABLE_AND_FULLCHIP_SUPPORT 0 NO_PIN_OUT 0 NO_POF 0 NO_ROUTING 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PRE_ND5_L_FINALITY 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 QPA_USES_PAN2 1 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRES_TLG 0 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 1 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_ADVANCED_SECURITY 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_EASIC 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 1 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_PARTIAL_MIGRATION 0 SUPPORTS_PSEUDO_LATCHES_ONLY 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORTS_VID_ALGORITHM 1 SUPPORT_HBM_IN_EPE 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_MULTIPLE_PAD_PER_PIN 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DMF_TIMING 0 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_FAMILY_PART_INFO 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_ANNOTATION_FOR_LAB_OUTPUTS 1 USES_LIBERTY_ANNOTATION_FOR_M20K_DSP_OUTPUTS 1 USES_LIBERTY_TIMING 0 USES_MULTIPLE_VID_VOLTAGES 0 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_SPECIFIC_DEV_FILES 0 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USES_TIMING_ROUTING_DELAYS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USE_VIRTUAL_DEV_NAME_FOR_FDI 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 VERMEER_USES_TSUNAMI_DIE 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR" type="string">
- <ipxact:name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE" type="string">
- <ipxact:name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.CONTENTS_INFO" type="string">
- <ipxact:name>embeddedsw.CMacro.CONTENTS_INFO</ipxact:name>
- <ipxact:value>""</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.DUAL_PORT" type="string">
- <ipxact:name>embeddedsw.CMacro.DUAL_PORT</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE" type="string">
- <ipxact:name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</ipxact:name>
- <ipxact:value>AUTO</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.INIT_CONTENTS_FILE" type="string">
- <ipxact:name>embeddedsw.CMacro.INIT_CONTENTS_FILE</ipxact:name>
- <ipxact:value>onchip_memory_1_onchip_memory_1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.INIT_MEM_CONTENT" type="string">
- <ipxact:name>embeddedsw.CMacro.INIT_MEM_CONTENT</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.INSTANCE_ID" type="string">
- <ipxact:name>embeddedsw.CMacro.INSTANCE_ID</ipxact:name>
- <ipxact:value>NONE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED" type="string">
- <ipxact:name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.RAM_BLOCK_TYPE" type="string">
- <ipxact:name>embeddedsw.CMacro.RAM_BLOCK_TYPE</ipxact:name>
- <ipxact:value>AUTO</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.READ_DURING_WRITE_MODE" type="string">
- <ipxact:name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</ipxact:name>
- <ipxact:value>DONT_CARE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.SINGLE_CLOCK_OP" type="string">
- <ipxact:name>embeddedsw.CMacro.SINGLE_CLOCK_OP</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.SIZE_MULTIPLE" type="string">
- <ipxact:name>embeddedsw.CMacro.SIZE_MULTIPLE</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.SIZE_VALUE" type="string">
- <ipxact:name>embeddedsw.CMacro.SIZE_VALUE</ipxact:name>
- <ipxact:value>4096</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.CMacro.WRITABLE" type="string">
- <ipxact:name>embeddedsw.CMacro.WRITABLE</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR" type="string">
- <ipxact:name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</ipxact:name>
- <ipxact:value>SIM_DIR</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.GENERATE_DAT_SYM" type="string">
- <ipxact:name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.GENERATE_HEX" type="string">
- <ipxact:name>embeddedsw.memoryInfo.GENERATE_HEX</ipxact:name>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.HAS_BYTE_LANE" type="string">
- <ipxact:name>embeddedsw.memoryInfo.HAS_BYTE_LANE</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.HEX_INSTALL_DIR" type="string">
- <ipxact:name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</ipxact:name>
- <ipxact:value>QPF_DIR</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH" type="string">
- <ipxact:name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</ipxact:name>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.memoryInfo.MEM_INIT_FILENAME" type="string">
- <ipxact:name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</ipxact:name>
- <ipxact:value>onchip_memory_1_onchip_memory_1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="postgeneration.simulation.init_file.param_name" type="string">
- <ipxact:name>postgeneration.simulation.init_file.param_name</ipxact:name>
- <ipxact:value>INIT_FILE</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="postgeneration.simulation.init_file.type" type="string">
- <ipxact:name>postgeneration.simulation.init_file.type</ipxact:name>
- <ipxact:value>MEM_INIT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>AGFB014R24A2E2VR0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Agilex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>s1</key>
- <value>
- <connectionPointName>s1</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="clk1" altera:internal="onchip_memory_1.clk1" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset1" altera:internal="onchip_memory_1.reset1" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="reset" altera:internal="reset"></altera:port_mapping>
- <altera:port_mapping altera:name="reset_req" altera:internal="reset_req"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="s1" altera:internal="onchip_memory_1.s1" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping>
- <altera:port_mapping altera:name="byteenable" altera:internal="byteenable"></altera:port_mapping>
- <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping>
- <altera:port_mapping altera:name="clken" altera:internal="clken"></altera:port_mapping>
- <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="write" altera:internal="write"></altera:port_mapping>
- <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/source/ip/pcie_ed/pcie_ed_clock_bridge_0.ip b/source/ip/pcie_ed/pcie_ed_clock_bridge_0.ip
deleted file mode 100644
index c0022b7..0000000
--- a/source/ip/pcie_ed/pcie_ed_clock_bridge_0.ip
+++ /dev/null
@@ -1,343 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>pcie_ed_clock_bridge_0</ipxact:library>
- <ipxact:name>clock_bridge_0</ipxact:name>
- <ipxact:version>19.2.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>in_clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>in_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>out_clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="21.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="21.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>out_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:master></ipxact:master>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedDirectClock" type="string">
- <ipxact:name>associatedDirectClock</ipxact:name>
- <ipxact:displayName>Associated direct clock</ipxact:displayName>
- <ipxact:value>in_clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>100000000</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="clockRateKnown" type="bit">
- <ipxact:name>clockRateKnown</ipxact:name>
- <ipxact:displayName>Clock rate known</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>altera_clock_bridge</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>in_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>out_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>pcie_ed_clock_bridge_0</ipxact:library>
- <ipxact:name>altera_clock_bridge</ipxact:name>
- <ipxact:version>19.2.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="DERIVED_CLOCK_RATE" type="longint">
- <ipxact:name>DERIVED_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Derived clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="EXPLICIT_CLOCK_RATE" type="longint">
- <ipxact:name>EXPLICIT_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Explicit clock rate</ipxact:displayName>
- <ipxact:value>100000000</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="NUM_CLOCK_OUTPUTS" type="int">
- <ipxact:name>NUM_CLOCK_OUTPUTS</ipxact:name>
- <ipxact:displayName>Number of Clock Outputs</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>AGFB014R24A2E2VR0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Agilex</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Agilex";
- type = "String";
- }
- }
- element clock_bridge_0
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>in_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>in_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>out_clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>out_clk</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>in_clk</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>in_clk</key>
- <value>
- <connectionPointName>in_clk</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>0</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>out_clk</key>
- <value>
- <connectionPointName>out_clk</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="in_clk" altera:internal="clock_bridge_0.in_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="out_clk" altera:internal="clock_bridge_0.out_clk" altera:type="clock" altera:dir="start">
- <altera:port_mapping altera:name="out_clk" altera:internal="out_clk"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/source/pcie_ed.qsys b/source/pcie_ed.qsys
index 0800f42..fa784b5 100644
--- a/source/pcie_ed.qsys
+++ b/source/pcie_ed.qsys
@@ -18,35 +18,11 @@
type = "int";
}
}
- element clock_bridge_100m
- {
- datum _sortIndex
- {
- value = "1";
- type = "int";
- }
- }
- element i2c_master_0
- {
- datum _sortIndex
- {
- value = "8";
- type = "int";
- }
- }
- element i2c_master_0.avalon_i2c_slave
- {
- datum baseAddress
- {
- value = "8224";
- type = "String";
- }
- }
element jtag_master
{
datum _sortIndex
{
- value = "3";
+ value = "2";
type = "int";
}
datum sopceditor_expanded
@@ -55,43 +31,11 @@
type = "boolean";
}
}
- element onchip_memory_0
- {
- datum _sortIndex
- {
- value = "4";
- type = "int";
- }
- }
- element onchip_memory_0.s1
- {
- datum baseAddress
- {
- value = "0";
- type = "String";
- }
- }
- element onchip_memory_1
- {
- datum _sortIndex
- {
- value = "5";
- type = "int";
- }
- }
- element onchip_memory_1.s1
- {
- datum baseAddress
- {
- value = "4096";
- type = "String";
- }
- }
element pio_out
{
datum _sortIndex
{
- value = "6";
+ value = "3";
type = "int";
}
datum sopceditor_expanded
@@ -112,7 +56,7 @@
{
datum _sortIndex
{
- value = "7";
+ value = "4";
type = "int";
}
}
@@ -128,7 +72,7 @@
{
datum _sortIndex
{
- value = "2";
+ value = "1";
type = "int";
}
}
@@ -173,17 +117,7 @@
internal="reset_bridge.in_reset"
type="reset"
dir="end" />
- <interface
- name="clock_100_in_clk"
- internal="clock_bridge_100m.in_clk"
- type="clock"
- dir="end" />
<interface name="hip_serial" internal="DUT.hip_serial" type="conduit" dir="end" />
- <interface
- name="i2c_master_0_scl_sda"
- internal="i2c_master_0.scl_sda"
- type="conduit"
- dir="end" />
<interface
name="pcie_ninit_done"
internal="DUT.ninit_done"
@@ -195,11 +129,7 @@
internal="pio_out.external_connection"
type="conduit"
dir="end" />
- <interface
- name="pio_reset"
- internal="pio_reset.external_connection"
- type="conduit"
- dir="end" />
+ <interface name="pio_reset" internal="pio_reset.external_connection" />
<interface name="refclk0" internal="DUT.refclk0" type="clock" dir="end" />
<interface name="refclk1" internal="DUT.refclk1" type="clock" dir="end" />
<module name="DUT" kind="altera_generic_component" version="1.0" enabled="1">
@@ -3724,7 +3654,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="clock_bridge_100m"
+ name="jtag_master"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -3732,12 +3662,12 @@
<boundary>
<interfaces>
<interface>
- <name>in_clk</name>
+ <name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>in_clk</name>
+ <name>clk_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
@@ -3766,14 +3696,14 @@
</parameters>
</interface>
<interface>
- <name>out_clk</name>
- <type>clock</type>
- <isStart>true</isStart>
+ <name>clk_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>out_clk</name>
- <role>clk</role>
- <direction>Output</direction>
+ <name>clk_reset_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -3786,210 +3716,24 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedDirectClock</key>
- <value>in_clk</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_clock_bridge</className>
- <version>19.2.0</version>
- <displayName>Clock Bridge Intel FPGA IP</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>DERIVED_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>in_clk</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>in_clk</key>
- <value>
- <connectionPointName>in_clk</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>0</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>out_clk</key>
- <value>
- <connectionPointName>out_clk</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>in_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>in_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>out_clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>out_clk</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>in_clk</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>pcie_ed_clock_bridge_0</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>pcie_ed_clock_bridge_0</fileSetName>
- <fileSetFixedName>pcie_ed_clock_bridge_0</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>pcie_ed_clock_bridge_0</fileSetName>
- <fileSetFixedName>pcie_ed_clock_bridge_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>pcie_ed_clock_bridge_0</fileSetName>
- <fileSetFixedName>pcie_ed_clock_bridge_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>pcie_ed_clock_bridge_0</fileSetName>
- <fileSetFixedName>pcie_ed_clock_bridge_0</fileSetFixedName>
- <fileSetKind>CDC</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hdlParameters"><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/pcie_ed/pcie_ed_clock_bridge_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="i2c_master_0"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
<interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
+ <name>master_reset</name>
+ <type>reset</type>
+ <isStart>true</isStart>
<ports>
<port>
- <name>wb_clk_i</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>master_reset_reset</name>
+ <role>reset</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -4002,3118 +3746,66 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_rst_i</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>avalon_i2c_slave</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_adr_i</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_dat_i</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_dat_o</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_we_i</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_stb_i</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_ack_o</name>
- <role>waitrequest_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_inta_o</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>i2c_master_0.avalon_i2c_slave</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>scl_sda</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>scl_pad_io</name>
- <role>scl</role>
- <direction>Bidir</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>sda_pad_io</name>
- <role>sda</role>
- <direction>Bidir</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>opencores_i2c</className>
- <version>1.0</version>
- <displayName>opencores_i2c</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors/>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>avalon_i2c_slave</key>
- <value>
- <connectionPointName>avalon_i2c_slave</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='avalon_i2c_slave' start='0x0' end='0x20' datawidth='8' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>5</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>8</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_clk_i</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_rst_i</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>avalon_i2c_slave</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_adr_i</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_dat_i</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_dat_o</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_we_i</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_stb_i</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>wb_ack_o</name>
- <role>waitrequest_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>wb_inta_o</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>i2c_master_0.avalon_i2c_slave</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>scl_sda</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>scl_pad_io</name>
- <role>scl</role>
- <direction>Bidir</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>sda_pad_io</name>
- <role>sda</role>
- <direction>Bidir</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>i2c_master_0</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>i2c_master_0</fileSetName>
- <fileSetFixedName>i2c_master_0</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>i2c_master_0</fileSetName>
- <fileSetFixedName>i2c_master_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>i2c_master_0</fileSetName>
- <fileSetFixedName>i2c_master_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>i2c_master_0</fileSetName>
- <fileSetFixedName>i2c_master_0</fileSetFixedName>
- <fileSetKind>CDC</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hdlParameters"><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/pcie_ed/i2c_master_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="jtag_master"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_reset_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>master_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>master_reset_reset</name>
- <role>reset</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>none</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>master</name>
- <type>avalon</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>master_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_write</name>
- <role>write</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_writedata</name>
- <role>writedata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_byteenable</name>
- <role>byteenable</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>debug.controlledBy</key>
- <value>in_stream</value>
- </entry>
- <entry>
- <key>debug.providesServices</key>
- <value>master</value>
- </entry>
- <entry>
- <key>debug.typeName</key>
- <value>altera_jtag_avalon_master.master</value>
- </entry>
- <entry>
- <key>debug.visible</key>
- <value>true</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>adaptsTo</key>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>dBSBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamReads</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamWrites</key>
- <value>false</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isAsynchronous</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isReadable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isWriteable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_jtag_avalon_master</className>
- <version>19.1</version>
- <displayName>JTAG to Avalon Master Bridge Intel FPGA IP</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE_FAMILY</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FAMILY</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>COMPONENT_CLOCK</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>clock</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos/>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_reset_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>master_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>master_reset_reset</name>
- <role>reset</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>none</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>master</name>
- <type>avalon</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>master_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_write</name>
- <role>write</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_writedata</name>
- <role>writedata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>master_byteenable</name>
- <role>byteenable</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>debug.controlledBy</key>
- <value>in_stream</value>
- </entry>
- <entry>
- <key>debug.providesServices</key>
- <value>master</value>
- </entry>
- <entry>
- <key>debug.typeName</key>
- <value>altera_jtag_avalon_master.master</value>
- </entry>
- <entry>
- <key>debug.visible</key>
- <value>true</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>adaptsTo</key>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>clk_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>dBSBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamReads</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamWrites</key>
- <value>false</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isAsynchronous</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isReadable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isWriteable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>jtag_master</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>jtag_master</fileSetName>
- <fileSetFixedName>jtag_master</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>jtag_master</fileSetName>
- <fileSetFixedName>jtag_master</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>jtag_master</fileSetName>
- <fileSetFixedName>jtag_master</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>jtag_master</fileSetName>
- <fileSetFixedName>jtag_master</fileSetFixedName>
- <fileSetKind>CDC</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hdlParameters"><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/pcie_ed/jtag_master.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap>
- <entry>
- <key>debug.hostConnection</key>
- <value>type jtag id 110:132</value>
- </entry>
- </assignmentValueMap>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="onchip_memory_0"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s2</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address2</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>chipselect2</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>clken2</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>write2</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>readdata2</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>writedata2</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>byteenable2</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_avalon_onchip_memory2</className>
- <version>19.3.0</version>
- <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>autoInitializationFileName</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>UNIQUE_ID</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFamily</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FAMILY</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFeatures</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FEATURES</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>s1</key>
- <value>
- <connectionPointName>s1</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>s2</key>
- <value>
- <connectionPointName>s2</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='s2' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
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- <assignmentValueMap>
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- <entry>
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- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
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- <key>addressAlignment</key>
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- <entry>
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- <entry>
- <key>associatedClock</key>
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- <entry>
- <key>associatedReset</key>
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- <entry>
- <key>bitsPerSymbol</key>
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- <entry>
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- <entry>
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- <entry>
- <key>isFlash</key>
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- <entry>
- <key>isMemoryDevice</key>
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- <entry>
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- <entry>
- <key>linewrapBursts</key>
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- <entry>
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- <entry>
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- <entry>
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- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
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- <entry>
- <key>prSafe</key>
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- </entry>
- <entry>
- <key>printableDevice</key>
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- <entry>
- <key>readLatency</key>
- <value>1</value>
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- <entry>
- <key>readWaitTime</key>
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- <entry>
- <key>registerIncomingSignals</key>
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- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
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- <entry>
- <key>setupTime</key>
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- <entry>
- <key>timingUnits</key>
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- <entry>
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- <entry>
- <key>waitrequestAllowance</key>
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- <entry>
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- <entry>
- <key>writeWaitStates</key>
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- <entry>
- <key>writeWaitTime</key>
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- </parameters>
- </interface>
- <interface>
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- <width>1</width>
- <lowerBound>0</lowerBound>
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- <terminationValue>0</terminationValue>
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- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
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- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
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- <type>avalon</type>
- <isStart>false</isStart>
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- <port>
- <name>address2</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>chipselect2</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>clken2</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>write2</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>readdata2</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>writedata2</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>byteenable2</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
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- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
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- <entry>
- <key>addressSpan</key>
- <value>4096</value>
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- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
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- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
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- <entry>
- <key>bridgedAddressOffset</key>
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- <entry>
- <key>bridgesToMaster</key>
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- <entry>
- <key>burstOnBurstBoundariesOnly</key>
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- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
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- <entry>
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- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
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- <entry>
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- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
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- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
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- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
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- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
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- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
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- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
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- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>onchip_memory_0</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>onchip_memory_0</fileSetName>
- <fileSetFixedName>onchip_memory_0</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>onchip_memory_0</fileSetName>
- <fileSetFixedName>onchip_memory_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>onchip_memory_0</fileSetName>
- <fileSetFixedName>onchip_memory_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>onchip_memory_0</fileSetName>
- <fileSetFixedName>onchip_memory_0</fileSetFixedName>
- <fileSetKind>CDC</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hdlParameters"><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/pcie_ed/onchip_memory_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CONTENTS_INFO</key>
- <value>""</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DUAL_PORT</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
- <value>onchip_memory_0_onchip_memory_0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INSTANCE_ID</key>
- <value>NONE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
- <value>DONT_CARE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_VALUE</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.WRITABLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
- <value>SIM_DIR</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
- <value>QPF_DIR</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
- <value>onchip_memory_0_onchip_memory_0</value>
- </entry>
- <entry>
- <key>postgeneration.simulation.init_file.param_name</key>
- <value>INIT_FILE</value>
- </entry>
- <entry>
- <key>postgeneration.simulation.init_file.type</key>
- <value>MEM_INIT</value>
- </entry>
- </assignmentValueMap>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="onchip_memory_1"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedDirectReset</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedResetSinks</key>
+ <value>none</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>s1</name>
+ <name>master</name>
<type>avalon</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>address</name>
+ <name>master_address</name>
<role>address</role>
- <direction>Input</direction>
- <width>10</width>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>clken</name>
- <role>clken</role>
+ <name>master_readdata</name>
+ <role>readdata</role>
<direction>Input</direction>
- <width>1</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
+ <name>master_read</name>
+ <role>read</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>write</name>
+ <name>master_write</name>
<role>write</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>readdata</name>
- <role>readdata</role>
+ <name>master_writedata</name>
+ <role>writedata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
@@ -7121,18 +3813,27 @@
<terminationValue>0</terminationValue>
</port>
<port>
- <name>writedata</name>
- <role>writedata</role>
+ <name>master_waitrequest</name>
+ <role>waitrequest</role>
<direction>Input</direction>
- <width>32</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>byteenable</name>
- <role>byteenable</role>
+ <name>master_readdatavalid</name>
+ <role>readdatavalid</role>
<direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ <terminationValue>0</terminationValue>
+ </port>
+ <port>
+ <name>master_byteenable</name>
+ <role>byteenable</role>
+ <direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -7142,40 +3843,35 @@
<assignments>
<assignmentValueMap>
<entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
+ <key>debug.controlledBy</key>
+ <value>in_stream</value>
</entry>
<entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
+ <key>debug.providesServices</key>
+ <value>master</value>
</entry>
<entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <key>debug.typeName</key>
+ <value>altera_jtag_avalon_master.master</value>
</entry>
<entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <key>debug.visible</key>
+ <value>true</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
+ <key>adaptsTo</key>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
<entry>
<key>addressUnits</key>
- <value>WORDS</value>
+ <value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
@@ -7183,23 +3879,16 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk1</value>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset1</value>
+ <value>clk_reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
@@ -7213,8 +3902,16 @@
<value>false</value>
</entry>
<entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
+ <key>dBSBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamReads</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamWrites</key>
+ <value>false</value>
</entry>
<entry>
<key>holdTime</key>
@@ -7225,25 +3922,29 @@
<value>false</value>
</entry>
<entry>
- <key>isBigEndian</key>
+ <key>isAsynchronous</key>
<value>false</value>
</entry>
<entry>
- <key>isFlash</key>
+ <key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
- <key>isMemoryDevice</key>
- <value>true</value>
+ <key>isReadable</key>
+ <value>false</value>
</entry>
<entry>
- <key>isNonVolatileStorage</key>
+ <key>isWriteable</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
+ <entry>
+ <key>maxAddressWidth</key>
+ <value>32</value>
+ </entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
@@ -7260,29 +3961,17 @@
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
<entry>
<key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -7300,26 +3989,10 @@
<key>timingUnits</key>
<value>Cycles</value>
</entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
@@ -7327,110 +4000,55 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundary>
<originalModuleInfo>
- <className>altera_avalon_onchip_memory2</className>
- <version>19.3.0</version>
- <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+ <className>altera_jtag_avalon_master</className>
+ <version>19.1</version>
+ <displayName>JTAG to Avalon Master Bridge Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
- <parameterName>autoInitializationFileName</parameterName>
+ <parameterName>AUTO_DEVICE</parameterName>
<parameterType>java.lang.String</parameterType>
- <systemInfotype>UNIQUE_ID</systemInfotype>
+ <systemInfotype>DEVICE</systemInfotype>
</descriptor>
<descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFamily</parameterName>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFeatures</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FEATURES</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>s1</key>
- <value>
- <connectionPointName>s1</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>COMPONENT_CLOCK</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>clock</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos/>
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>clk1</name>
+ <name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
+ <name>clk_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
@@ -7459,49 +4077,116 @@
</parameters>
</interface>
<interface>
- <name>s1</name>
- <type>avalon</type>
+ <name>clk_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>address</name>
- <role>address</role>
+ <name>clk_reset_reset</name>
+ <role>reset</role>
<direction>Input</direction>
- <width>10</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>master_reset</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
<port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
+ <name>master_reset_reset</name>
+ <role>reset</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>none</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>master</name>
+ <type>avalon</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>master_address</name>
+ <role>address</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <terminationValue>0</terminationValue>
+ </port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>master_readdata</name>
+ <role>readdata</role>
<direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <terminationValue>0</terminationValue>
+ </port>
+ <port>
+ <name>master_read</name>
+ <role>read</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>write</name>
+ <name>master_write</name>
<role>write</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>readdata</name>
- <role>readdata</role>
+ <name>master_writedata</name>
+ <role>writedata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
@@ -7509,18 +4194,27 @@
<terminationValue>0</terminationValue>
</port>
<port>
- <name>writedata</name>
- <role>writedata</role>
+ <name>master_waitrequest</name>
+ <role>waitrequest</role>
<direction>Input</direction>
- <width>32</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
- <name>byteenable</name>
- <role>byteenable</role>
+ <name>master_readdatavalid</name>
+ <role>readdatavalid</role>
<direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ <terminationValue>0</terminationValue>
+ </port>
+ <port>
+ <name>master_byteenable</name>
+ <role>byteenable</role>
+ <direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -7530,40 +4224,35 @@
<assignments>
<assignmentValueMap>
<entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
+ <key>debug.controlledBy</key>
+ <value>in_stream</value>
</entry>
<entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
+ <key>debug.providesServices</key>
+ <value>master</value>
</entry>
<entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <key>debug.typeName</key>
+ <value>altera_jtag_avalon_master.master</value>
</entry>
<entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <key>debug.visible</key>
+ <value>true</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
+ <key>adaptsTo</key>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
<entry>
<key>addressUnits</key>
- <value>WORDS</value>
+ <value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
@@ -7571,22 +4260,16 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk1</value>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset1</value>
+ <value>clk_reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
- <entry>
- <key>bridgedAddressOffset</key>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
@@ -7600,8 +4283,16 @@
<value>false</value>
</entry>
<entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
+ <key>dBSBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamReads</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamWrites</key>
+ <value>false</value>
</entry>
<entry>
<key>holdTime</key>
@@ -7612,25 +4303,29 @@
<value>false</value>
</entry>
<entry>
- <key>isBigEndian</key>
+ <key>isAsynchronous</key>
<value>false</value>
</entry>
<entry>
- <key>isFlash</key>
+ <key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
- <key>isMemoryDevice</key>
- <value>true</value>
+ <key>isReadable</key>
+ <value>false</value>
</entry>
<entry>
- <key>isNonVolatileStorage</key>
+ <key>isWriteable</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
+ <entry>
+ <key>maxAddressWidth</key>
+ <value>32</value>
+ </entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
@@ -7647,29 +4342,17 @@
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
<entry>
<key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -7687,69 +4370,13 @@
<key>timingUnits</key>
<value>Cycles</value>
</entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
<entry>
<key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- <terminationValue>0</terminationValue>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
+ <value>0</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
@@ -7757,29 +4384,29 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>onchip_memory_1</hdlLibraryName>
+ <hdlLibraryName>jtag_master</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>onchip_memory_1</fileSetName>
- <fileSetFixedName>onchip_memory_1</fileSetFixedName>
+ <fileSetName>jtag_master</fileSetName>
+ <fileSetFixedName>jtag_master</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>onchip_memory_1</fileSetName>
- <fileSetFixedName>onchip_memory_1</fileSetFixedName>
+ <fileSetName>jtag_master</fileSetName>
+ <fileSetFixedName>jtag_master</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>onchip_memory_1</fileSetName>
- <fileSetFixedName>onchip_memory_1</fileSetFixedName>
+ <fileSetName>jtag_master</fileSetName>
+ <fileSetFixedName>jtag_master</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>onchip_memory_1</fileSetName>
- <fileSetFixedName>onchip_memory_1</fileSetFixedName>
+ <fileSetName>jtag_master</fileSetName>
+ <fileSetFixedName>jtag_master</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
</fileSet>
@@ -7787,104 +4414,12 @@
</generationInfoDefinition>]]></parameter>
<parameter name="hdlParameters"><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/pcie_ed/onchip_memory_1.ip</parameter>
+ <parameter name="logicalView">ip/pcie_ed/jtag_master.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
- <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CONTENTS_INFO</key>
- <value>""</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DUAL_PORT</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
- <value>onchip_memory_1_onchip_memory_1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INSTANCE_ID</key>
- <value>NONE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
- <value>DONT_CARE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_VALUE</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.WRITABLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
- <value>SIM_DIR</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
- <value>QPF_DIR</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
- <value>onchip_memory_1_onchip_memory_1</value>
- </entry>
- <entry>
- <key>postgeneration.simulation.init_file.param_name</key>
- <value>INIT_FILE</value>
- </entry>
- <entry>
- <key>postgeneration.simulation.init_file.type</key>
- <value>MEM_INIT</value>
+ <key>debug.hostConnection</key>
+ <value>type jtag id 110:132</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
@@ -9011,7 +5546,7 @@
name="pio_reset"
kind="altera_generic_component"
version="1.0"
- enabled="1">
+ enabled="0">
<parameter name="componentDefinition"><![CDATA[<componentDefinition>
<boundary>
<interfaces>
@@ -10416,75 +6951,6 @@
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
- <connection
- kind="avalon"
- version="21.2"
- start="DUT.d2hdm_master"
- end="onchip_memory_0.s2">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableAllPipelines" value="FALSE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.optimizeRdFifoSize" value="FALSE" />
- <parameter name="qsys_mm.piplineType" value="PIPELINE_STAGE" />
- <parameter name="qsys_mm.syncResets" value="TRUE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
- <connection
- kind="avalon"
- version="21.2"
- start="DUT.h2ddm_master"
- end="onchip_memory_0.s2">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableAllPipelines" value="FALSE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.optimizeRdFifoSize" value="FALSE" />
- <parameter name="qsys_mm.piplineType" value="PIPELINE_STAGE" />
- <parameter name="qsys_mm.syncResets" value="TRUE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
- <connection
- kind="avalon"
- version="21.2"
- start="jtag_master.master"
- end="i2c_master_0.avalon_i2c_slave">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2020" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableAllPipelines" value="TRUE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.optimizeRdFifoSize" value="FALSE" />
- <parameter name="qsys_mm.piplineType" value="PIPELINE_STAGE" />
- <parameter name="qsys_mm.syncResets" value="TRUE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
<connection
kind="avalon"
version="21.2"
@@ -10531,52 +6997,6 @@
<parameter name="qsys_mm.syncResets" value="TRUE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
- <connection
- kind="avalon"
- version="21.2"
- start="jtag_master.master"
- end="onchip_memory_0.s1">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableAllPipelines" value="TRUE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.optimizeRdFifoSize" value="FALSE" />
- <parameter name="qsys_mm.piplineType" value="PIPELINE_STAGE" />
- <parameter name="qsys_mm.syncResets" value="TRUE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
- <connection
- kind="avalon"
- version="21.2"
- start="DUT.rx_pio_master"
- end="i2c_master_0.avalon_i2c_slave">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2020" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableAllPipelines" value="TRUE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.optimizeRdFifoSize" value="FALSE" />
- <parameter name="qsys_mm.piplineType" value="PIPELINE_STAGE" />
- <parameter name="qsys_mm.syncResets" value="TRUE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
<connection
kind="avalon"
version="21.2"
@@ -10623,52 +7043,6 @@
<parameter name="qsys_mm.syncResets" value="TRUE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
- <connection
- kind="avalon"
- version="21.2"
- start="DUT.rx_pio_master"
- end="onchip_memory_0.s1">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableAllPipelines" value="TRUE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.optimizeRdFifoSize" value="FALSE" />
- <parameter name="qsys_mm.piplineType" value="PIPELINE_STAGE" />
- <parameter name="qsys_mm.syncResets" value="TRUE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
- <connection
- kind="avalon"
- version="21.2"
- start="DUT.rx_pio_master"
- end="onchip_memory_1.s1">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x1000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableAllPipelines" value="TRUE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.optimizeRdFifoSize" value="FALSE" />
- <parameter name="qsys_mm.piplineType" value="PIPELINE_STAGE" />
- <parameter name="qsys_mm.syncResets" value="TRUE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
<connection kind="clock" version="21.2" start="DUT.app_clk" end="pio_out.clk" />
<connection
kind="clock"
@@ -10676,27 +7050,7 @@
start="DUT.app_clk"
end="reset_bridge.clk" />
<connection kind="clock" version="21.2" start="DUT.app_clk" end="pio_reset.clk" />
- <connection
- kind="clock"
- version="21.2"
- start="DUT.app_clk"
- end="i2c_master_0.clk" />
<connection kind="clock" version="21.2" start="DUT.app_clk" end="jtag_master.clk" />
- <connection
- kind="clock"
- version="21.2"
- start="DUT.app_clk"
- end="onchip_memory_0.clk1" />
- <connection
- kind="clock"
- version="21.2"
- start="DUT.app_clk"
- end="onchip_memory_1.clk1" />
- <connection
- kind="reset"
- version="21.2"
- start="DUT.app_nreset_status"
- end="i2c_master_0.clk_reset" />
<connection
kind="reset"
version="21.2"
@@ -10707,26 +7061,11 @@
version="21.2"
start="DUT.app_nreset_status"
end="pio_reset.reset" />
- <connection
- kind="reset"
- version="21.2"
- start="DUT.app_nreset_status"
- end="onchip_memory_0.reset1" />
- <connection
- kind="reset"
- version="21.2"
- start="DUT.app_nreset_status"
- end="onchip_memory_1.reset1" />
<connection
kind="reset"
version="21.2"
start="reset_bridge.out_reset"
end="jtag_master.clk_reset" />
- <connection
- kind="reset"
- version="21.2"
- start="reset_bridge.out_reset"
- end="i2c_master_0.clk_reset" />
<connection
kind="reset"
version="21.2"
@@ -10737,16 +7076,6 @@
version="21.2"
start="reset_bridge.out_reset"
end="pio_reset.reset" />
- <connection
- kind="reset"
- version="21.2"
- start="reset_bridge.out_reset"
- end="onchip_memory_0.reset1" />
- <connection
- kind="reset"
- version="21.2"
- start="reset_bridge.out_reset"
- end="onchip_memory_1.reset1" />
<wireLevelConnections>
<expression value="DUT.p0_pld_warm_rst_rdy_i=1'b1" enabled="1" />
</wireLevelConnections>
--
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