From f292700b32e0d1c280201a5ecb96e37efbe02316 Mon Sep 17 00:00:00 2001
From: Baptiste Lefevre <baptiste.lefevre@etu.emse.fr>
Date: Mon, 6 Sep 2021 15:55:32 +0200
Subject: [PATCH] Change jtag clock to 350MHz(pcie app clock)
---
source/pcie_ed.qsys | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/source/pcie_ed.qsys b/source/pcie_ed.qsys
index 4b91d41..0800f42 100644
--- a/source/pcie_ed.qsys
+++ b/source/pcie_ed.qsys
@@ -10681,6 +10681,7 @@
version="21.2"
start="DUT.app_clk"
end="i2c_master_0.clk" />
+ <connection kind="clock" version="21.2" start="DUT.app_clk" end="jtag_master.clk" />
<connection
kind="clock"
version="21.2"
@@ -10691,11 +10692,6 @@
version="21.2"
start="DUT.app_clk"
end="onchip_memory_1.clk1" />
- <connection
- kind="clock"
- version="21.2"
- start="clock_bridge_100m.out_clk"
- end="jtag_master.clk" />
<connection
kind="reset"
version="21.2"
--
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