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v10

- merge startproject altera and xilinx files in 1 file
- automatize configuration.tcl file
- accept * in tool version to accept all

- improve READMEs
- add additional_assignments files

72ffcdc5 · minor fixes · Jun 07, 2024

- allow to define a list of FPGA compliant with the IP
- allow to define a list of versions for the compilation tool compliant with the IP

- simplify compilation scripts
- handle automatically .gitignore (for quartus)

v5.1

351941cf · fix sim script and add remove assignments for quartus · Mar 07, 2024

New versionning (ip will be vX.Y.Z.5) from that ip squelette version
improve scripts for Intel properly dealing with IPs generation

first version working for both Xilinx and Altera and tested successfully.

No filelist
Config & init files added
script path automatically dedected