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Tags

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  • 2.0.2

    643c5769 · fix typo · May 07, 2019
  • 2.0.1

    3d8113d8 · Attempt to fix problematic data capture and produce bitstream · Apr 10, 2019
  • 2.0

    91eac46c · updated firmware · Nov 22, 2018
  • 1.8

    1bb8abce · Tangled for omega tests and compiled · Jul 26, 2018
  • 1.7

    f651175d · documenting · Jul 21, 2018
  • 1.6.1

    f22d944c · Avoid slow control reset but at startup · Jul 10, 2018
  • 1.6

    54b457ec · Merge branch 'devel' · Jul 10, 2018
  • 1.5.4

    148c06b1 · prefer compressed bitstream · May 23, 2018
  • 1.5.3

    936a097a · Redimension fifos to use al fpga resources · Apr 02, 2018
  • 1.5.2

    dd0da5ff · Merge branch 'p2_params_reordering' · Mar 31, 2018
  • 1.5.1

    786e2787 · Merge branch 'boardid-optimize' · Mar 31, 2018
  • 1.5

    66004f18 · tangled for omega test and compiled · Mar 27, 2018
  • 1.4.2

    eff6328a · fixed issue in cati data capture · Dec 01, 2017
  • 1.4.1

    3bcfc1da · S-Curve : use falling edge, and not levels to compute · Nov 22, 2017
  • 1.4

    c6ce9271 · Merge branch 'format-v3' · Nov 21, 2017
  • 1.3

    305ef23d · removed multiplexor after catiroc module with altera · Nov 16, 2017
  • 1.2

    d950fd54 · xilinx: compiled project · Nov 15, 2017
  • 1.1

    2d39ce86 · Fixed doc un usb if vorg file · Sep 19, 2017
  • 1.0

    79e652f2 · fixed last commit · Aug 07, 2017
  • 0.9

    35d9c5de · discri 2 · Jun 18, 2017
  • 1
  • 2