Skip to content
Snippets Groups Projects
Commit 78a16c94 authored by Baptiste LEFEVRE's avatar Baptiste LEFEVRE
Browse files

first ok compilation

parent 92889795
No related branches found
No related tags found
1 merge request!1Baptiste dev
Hide whitespace changes
Inline Side-by-side
.gitignore
+ 1
− 0
View file @ 78a16c94
......@@ -7,3 +7,4 @@
sources/ip/data_bus/data_bus_clock_in/
sources/ip/data_bus/data_bus_pio_0/
sources/ip/data_bus/data_bus_reset_in/
sources/data_bus/
scripts/set_project_files.tcl
+ 1
− 1
View file @ 78a16c94
......@@ -5,7 +5,7 @@ set_global_assignment -name VERILOG_FILE $project_git/agilex_LL_firmware/sources
set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_clock_in.ip
set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_reset_i.ip
set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_reset_in.ip
set_global_assignment -name IP_FILE $project_git/agilex_LL_firmware/sources/ip/data_bus/data_bus_pio_0.ip
set_global_assignment -name QSYS_FILE $project_git/agilex_LL_firmware/sources/data_bus.qsys
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment